The invention relates to a nonvolatile memory cell arrangement.
In modern semiconductor technology various approaches are being pursued in order to improve the performance and the storage capacities of memory cell arrangements. These approaches consist not only in the development of novel types of transistors, but also in a continued scaling and miniaturization of the field effect transistors and in novel memory cell architectures.
One such type of transistor is a fin field effect transistor (FinFET), for example, in which the channel region between two source/drain regions is realized as a semiconductor fin, above which a gate region is deposited. The storage capacity of a memory cell arrangement is improved with a fin field effect transistor on account of the small space requirement for realizing the latter.
For high-density nonvolatile data storage, floating gate based NAND memory architectures are commercially predominant at the present time. Advantages of a NAND memory arrangement include the low costs per memory bit, in particular for so-called multilevel storage, the simple fabrication process and also a good scalability of the memory cells for F>50 nm, where F denotes the side length of the memory cell array and is essentially determined by the technology.
FIG. 1 illustrates a memory cell arrangement 100 in NAND circuitry interconnection. The NAND memory cell arrangement 100 has a plurality of memory cells 109 each having a memory transistor 102. Each memory transistor 102 has a storage layer 103 in which electrical charge carriers can be stored in nonvolatile fashion. Furthermore, the NAND memory cell arrangement 100 is provided with a first control transistor 101, a second control transistor 104 and also a plurality of gate terminal connecting lines 105 (also referred to as word lines) arranged in parallel, a source terminal connecting line 106, a supply line 107 and a contact location 108 on the supply line 107. The memory transistors 102 are connected in series with one another by means of their source/drain terminal and are arranged between the first control transistor 101 and the second control transistor 104. The first control transistor 101 is electrically connected by its drain terminal to the supply line 107 by means of the contact location 108 and by its source terminal to the drain terminal of a first memory transistor 102 of the plurality of memory transistors 102. The source terminal of a respective memory transistor 102 is connected to a respective drain terminal of the respectively adjacent memory transistor 102. The second control transistor 104 is connected by its source terminal to the source line 106. The control transistors 101, 104 and the memory transistors 102 are in each case connected by their gate terminal to a respective gate terminal connecting line 105.
E. S. Cho, T. Y. Kim, C. Lee, Optimized Cell Structure for FinFet Array Flash Memory, 34th European Solid-State Device Research Conference, 2004, pages 289-292 discloses a NOR memory arrangement in which the memory transistors are constructed as floating gate fin field effect transistors. In the case of the floating gate fin field effect transistor described in E. S. Cho, T. Y. Kim, C. Lee, Optimized Cell Structure for FinFet Array Flash Memory, 34th European Solid-State Device Research Conference, 2004, pages 289-292, an ONO layer sequence (silicon dioxide/silicon nitride/silicon dioxide) is provided for the electrical insulation of the floating gate made of polysilicon.
However, considerable difficulties are to be expected for F<50 nm on account of increasing capacitive floating gate-to-floating gate interactions or couplings, and also an impaired gate controllability of the floating gate and a punch-through effect as a result of a read drain voltage or low read currents.
Furthermore, I. Fujiwara et al, 0.13 μm MONOS single transistor memory cells with separated source lines, IEEE, International Electron Device Meeting, Technical Digest, 1998 describes a MONOS 6F2 memory cell arrangement having source lines that are referred to therein as “winding source lines”.
US 2002/0036927 A1 describes a memory cell arrangement in matrix form in which the source lines are arranged in one plane and the bit lines run perpendicular to the source lines and are arranged in a different plane than the source lines.
DE 102 41 171 A1 describes a word and bit line arrangement for a FINFET semiconductor memory. The bit lines are connected to a multiplicity of contact regions and run diagonally with respect to the columns of the transistors. The longitudinal axes of first bit line segments run parallel to a first bit line direction and the longitudinal axes of second bit line segments run parallel to a second bit line direction, the second bit line direction being rotated relative to the first bit line direction.
U.S. Pat. No. 6,617,632 B2 likewise describes a memory cell arrangement whose memory cells are arranged in matrix form. In order to prevent the punch-through effect, the source and drain regions of the memory transistors are in each case surrounded by punch-through-stop layers.